CSCI 320 Computer Architecture
Professor Dan Hyde
Fall 2007
Handouts:
Assignments:
Homework 1 due Wednesday 29 August
Homework 2 due Monday 17 September
Homework 3 due Wednesday 3 October
Homework 4 due Monday 12 November
Homework 5 due Monday 10 December
Labs:
28 August, Lab 1 Introduction to Verilog HDL
4 September, Lab 2 Addressing Modes for Ultra
11 September, Lab 3 Additional Instructions for Ultra
18 September, Lab 4 Performance of Your Ultra
25 September, Lab 5 Integer Multiply Instruction
2 October, Lab 6 Design of a Ripple Carry Adder
9 October, Lab 7 Instruction Lookahead
30 October, Lab 8 Branch Prediction
6 November, Lab 9 Cache Simulation
13 November, Lab 10 Cache Memory I
20 November, Lab 11 Cache Memory II
Resources:
Last modified: November 28, 2007