Instructor: Professor Dan Hyde, 338 Dana, x71281, hyde at bucknell.edu
Office Hours: MW 3-4; T 4-5
Text: Hennessy, John L. and David A. Patterson, Computer Architecture: A Quantitative Approach, 4th edition, Morgan Kaufmann Publishers, 2007.
Course Web Site: http://www.eg.bucknell.edu/~cs320/2007-fall/
Introduction
This course builds on CSCI 206 Computer
Organization which is a
strict prerequisite. Both the
CSCI 206 text and our text are written
by the same authors. The authors assume that you have
read and studied their other text Computer Organization and Design:
The Hardware/Software Interface. Therefore, you should have
access to your CSCI 206 text. Hopefully you didn't sell it!
In this course, we will continue your study of digital computer
hardware design. The
objective
is to build on your understanding of the datapath of the MIPS RISC
processor/computer and look at design decisions made for other
processors. We will look at examples from desktop, server and
embedded processors, exploring instruction sets design, pipelines for
integer and floating point, and mechanisms to keep multiple execution
units occupied. We will look at cache and disk memory in
more detail and examine what design decisions are necessary for an I/O
system. We will then examine some of the challenges of making
multiprocessor environments useful. The textbook provides the reasons why computer
manufacturers such as INTEL are embarking on the multi-core roadmap which promises a
doubling of the number of processors on a chip every other year. The text also
examines the quantative basis for many decisions, showing how performance,
cost, etc. are determined.
While looking at the example advanced processors in class, you will
be doing actual design in lab. You will use a design tool called Verilog
that can describe and simulate the operation of a computer. Verilog
runs in the Linux environment. You will implement the datapath of a
processor much
like the MIPS RISC, adding new features week by week.
Undoubtedly, some of the decisions you make as you proceed will be
costly later!
Course Structure
This course will have written problem sets, labs, and projects. There will be one midterm exam, worth 25% of your final grade. There will be a final exam, worth 25% of your final grade. Every Friday we will have a ten minute quiz on material from the lectures and the text (total 10%). There will be frequent written problem sets during the semester for a total of 10% of your grade. There is also a weekly lab associated with the course(20%). The projects are 10% of your grade. Written assignments are to be prepared on 8.5"x11" paper. Multipe page assignments as well as lab assignments are to be stapler together.
Grading is as follows:
| Midterm exam and final exam |
50% |
| Lab |
20% |
| Written problem sets and projects |
20% |
| Quizzes |
10% |
Policies
Class and lab attendance is required and expected. If for some reason you can't make a class or lab, please send an email message to the instructor with a good reason before the class or lab.
Written problem sets are to be submitted at the beginning of class on the assigned due date. No late assignments will be accepted without prior permission of instructor. No work will be accepted after the solution has been discussed in class.
Work submitted must be your own, or that of a pair when permitted
as indicated on an assignment or project.
Unsolicited reading or copying of other student or faculty files is as wrong as looking at or removing papers from a student or faculty member's desk. Such academic dishonesty has been and will be referrred to the University Student Conduct Committee for appropriate punitive action (See Bucknell Student Handbook).