Use engineering paper and pencil. Neatness and intelligent layout count up to 10%.
1. Describe, in words your grandmother could understand, the following:
2. Construct a digital logic circuit, i.e., D flip flops, AND, OR and NOT gates, for the following computation (data path only):
reg [0:2] A;
A <= {A[1], A[2], A[0]};
3. Construct a timing diagram for problem 2 using leading-edge-triggered
D flip flops. Assume that the initial value of A is (1,
0, 0). Assume the computation is in an always construct and do
the computation three times, i. e., for three clock periods.
4. Construct the digital logic circuit (data path only) associated with both of the two computations below. Assume no busing.
reg [0:2] X, Y; #1 X <= ~X; #1 X <= Y;5. Construct the digital logic circuit for only the control unit of the following Verilog HDL sequence. Assume this is only a portion of the Verilog HDL sequence.
reg [0:3] A, B, X, Z;
reg a, b; // a and b are 1-bit registers
#1 a <= 1;
#1 while (a)
begin
if (b)
begin
#1 A <= X;
#1 B <= Z;
end
else
#1 Z <= A;
#1 X <= B;
end
6. Construct a digital logic circuit of the hardware realization of
both the
control unit and data path specified by the following Verilog HDL
description,
where a and b are flip flops and x is an input
line. Assume this is only a portion of the Verilog HDL sequence.
reg a, b;
wire x;
#1 a <= x | b;
while (x)
begin
#1 b <= x;
#1 b <= x & b;
end