In all the following exercises, assume a simple clock, i.e., we are NOT using a 2-phase clock as described in the text.

1. Given the pipelined MIPS instruction stream:

    	Instructions            Comments
           ADD R1,R2,R3            R1 <= R2+R3
           LW R4,200(R1)           R4 <= Mem[200+R1]
           SW 300(R1),R4           Mem[300+R1] <= R4
   

   a.) Assuming NO forwarding, what are the stalls due to data hazards? Draw an "IF-ID-EX-MEM-WB" diagram and show the stalls. Also, discuss why.

   b.) Assuming forwarding, what are the stalls due to data hazards? Draw an "IF-ID-EX-MEM-WB" diagram and show the stalls. Also, discuss why.

2. In the following MIPS instruction stream, find the data hazards which can not be removed by forwarding.

   	Instructions		Comments
   	ADD R1,R2,R3		R1 <= R2+R3
   	LW R4,200(R1)		R4 <= Mem[200+R1]
   	SW 300(R4),R1		Mem[300+R4] <= R1
           SUB R3,R2,R1            R3 <= R2-R1
   

   Rewrite the instruction stream to remove the data hazards by using the static scheduling technique.

3. In the following MIPS code, find the control hazards. Assume the branch penalty is one clock period. Assume forwarding.

   	Instructions		Comments
     LOOP: ADD R1,R2,R3		R1 <= R2+R3
   	LW R2,200(R1)		R2 <= Mem[200+R1]
   	BNEZ R1, LOOP           Branch to label LOOP if R1 != 0
           SUB R3,R2,R1            R3 <= R2-R1
   

   Rewrite the instruction code to remove the control hazards by using the delayed branch technique.