CS320 Computer Architecture

Also, don't be afraid to explore topics beyond the assigned exercises.

PURPOSE:

• Become familiar with the operations of the Verilog HDL and the veriwell simulator program.

• Use Verilog HDL to explore the design of a simple computer.

Reference: CSCI 320Computer Architecture Handbook on Verilog HDL by Professor Dan Hyde

Printing Verilog files

If a file has a .v extension, the Unix command a2ps assumes it is a Verilog file and formats the file for Verilog, e.g., bolds all reserved words. All Verilog files handed in for this course must be printed with a2ps.

Exercise #1 - Running the veriwell simulator.

Copy evenodd.v from ~cs320.  Run veriwell as follows:

veriwell evenodd.v -s

Use a period to have the program execute to the end.  Note that the results are correct.  Look at the code to see the correct way to initialize a binary value.

See the manual (p. 24 and following) on how to use the interactive mode for the program veriwell.

Start veriwell again and use a comma to single step through the execution.  (Note that the stop_at will not stop you at time step 2 when you are single stepping.)  Check out on how to look at variables values, etc. on page 25.

Use a single file for the hand-in for all six exercises in the lab. Save your file as a text file with the .v extension, to be printed later.  Make it obvious which section of the printout is which by using "dividers" or annotation between the exercises.  For this exercise describe what it does and how the evenodd.v program works. 

Exercise #2 - Coding and running a new program

Using your favorite editor, type in the Verilog HDL program on page 6 (Section 2.1) in CSCI 320 Computer Architecture Handbook on Verilog HDL. You do not need to type in all those comments. However, insert a comment for your name, course and date.

Correct your syntax errors and work with Veriwell until you have everything correct.

Copy and paste your working program and correct output to your text file.  Indicate in the file or by hand annotation how and why the output is correct.

Exercise #3 - Every Eighth One

Design the Verilog HDL code for a digital system where register B is a logical one for every eighth clock period. Register B should stay at a logical one for only one clock period then go back to zero for the other seven clock periods. The first time B is a logical one need not be eight clock periods from the start. Hand in a printout of the code and simulator output.

Remember, if you haven't figured out the algorithm, you won't be successful.

Exercise #4 - Circular left shift

Design the Verilog HDL for a digital system where the eight bit register A is initialized to 1 then is shifted one bit to the left every clock period. The left most bit should be wrapped around to the other end. Output of A should be in binary. Hand in a printout of the code and the simulator output.

Exercise #5 - Binary Coded Decimal

Design the Verilog HDL code for a digital system which counts from 0 to 9 in Binary Coded Decimal (BCD) over and over. BCD uses four bits and goes 0000, 0001, 0010, etc. up to 1001 (9). Output of counter should be in binary. Hand in a printout of the code and simulator output.

Exercise #6 - Ultra Simple CPU

You are to design the Verilog HDL control sequence for the ULTRA computer. The ULTRA is an ultra small computer to give you practice in the ideas of designing a CPU with the Verilog HDL notation.

ULTRA has a 64-word memory (MEM) where each word is one byte. The memory is synchronous to the CPU, and the CPU can read or write a word in one clock period. The memory can only be accessed through the memory address register (MA) and the memory data register (MD). To read from memory, you use

    MD <= MEM[MA];

    MEM[MA] <= MD;

00  LOAD M   loads the contents of memory word M into the accumulator.
01  STORE M  stores the contents of the accumulator in memory word M.
10  ADD M    adds the contents of memory word M to the contents of the accumulator.
11  JUMP M   jumps to location M in memory.

To get you started here are the declares needed for the program. The parameter statement in Verilog HDL allows you to name a constant.

	parameter clock = 1;
	reg [0:5] PC, MA;
	reg [0:7] AC, IR, MD;
	reg [0:7] MEM[0:63];     // 64 words of 8-bit memory

	#clock MA <= PC;

	initial begin: Init
		PC = 0;	// set program counter to 0
		MEM[0] = 8'b00000100; 	//Load 4
		// etc...
	end

HAND IN

The required program to be handed in is the following:

	Address	Contents
	0	Load  4
	1	Add   5
	2	Store 6
	3	Jump  1
	4	Data  1
	5	Data  2

Save a copy of the ULTRA code for a later lab.

Make sure you print the file containing all six exercises with the a2ps command and staple the sheets together.