Exercise #0: Continue your Design
Decisions Log
Copy the Verilog code of the ULTRA2 computer of the last exercise of Lab #2 to a new file called ULTRA3.v.
Before proceeding to today's Exercise #2 we want some confidence that your machine of Lab 2 is correct for last week's three exercises, i.e., in the process of doing an exercise did you screw up something of a previous exercise?
Comment out the "software" program of Lab 2 Exercise 3 and copy and paste the "software" program of Lab 2 Exercise 1 into your machine. Run and verify that your machine is correct. You may have to adjust the MEM locations outputted. If any errors, fix them.
Comment out the "software" program of Lab 2 Exercise 1 (that you just tested) and copy and paste the "software" program of Lab 2 Exercise 2 into your machine. Run and verify that your machine is correct. You may have to adjust the MEM locations outputted. If any errors, fix them.
After any repairs, re-run Lab 2 Ex 3.
Before proceeding to today's Exercise 2, make sure your machine can correctly run the three "software"programs of all three exercises. Document any changes that you needed to make in your design decisions log.
HAND IN
You do not need to hand in anything for this exercise but do not skip this step. This is a short lab, you will have time to do this testing.Exercise #2: Add Subtraction Instruction
Add the subtraction instruction to your Ultra3.
SUB R[i],R[j],R[k] R[i] <- R[j] - R[k]Assume negative numbers are represented in 2's complement. When a CPU uses the 2's complement representation of negative numbers, it does not need any subtraction hardware. This is one reason why 2's complement representation is so popular.
Therefore, for this lab, you can not use the Verilog operator "-". You must use your adder, i.e., the Verilog "+" operator, along with the appropriate conversion of 2's complement.
To test your ULTRA3 design, perform the following program where PC starts at 10.
3 DATA 2HAND IN
4 DATA 1
10 LOAD R1,3
11 LOAD R2,4
12 SUB R1,R1,R2
13 STORE R1,5
14 JUMP 12
Hand in Verilog code and output which demonstrates that
this portion of the ULTRA3 works properly. The output should include
all the registers and appropriate memory locations in hex format
(Use
%h). Also, use a $display to show the start of each
instruction. In the Verilog code include comments for each section,
e.g., //load. On the output(s), hand write comments
explaining what's happening and what you are testing to make it obvious
that it is working.
Exercise #3: Add Branch Instructions
Add three new branch instructions BEQ, BNE and BLT that branch PC relative if the two specified registers are equal, not equal and less than respectively.
BEQ R[i],R[j],d If R[i] = R[j], branch PC relative to dThe displacement d may be negative.
BNE R[i],R[j],d If R[i] != R[j], branch PC relative to d
BLT R[i],R[j],d If R[i] < R[j], branch PC relative to d
To test your ULTRA3 design, perform the following program where PC starts at 10.
3 DATA 2HAND IN
4 DATA 1
10 LOAD R1,3
11 LOAD R2,4
12 BNE R1,R2,2
13 ADD R1,R1,R2
14 STORE R1,5
15 ADD R1,R0,R2
16 BEQ R1,R2,2
17 JUMP 10
18 STORE R1,6
19 LoadI R1,4
20 BLT R2,R1,-6
21 JUMP 12
Hand in Verilog code and output which demonstrates that this portion of the ULTRA3 works properly. The output should include all the registers and appropriate memory locations in hex format (Use %h). Also, use a $display to show the start of each instruction. In the Verilog code include comments for each section, e.g., //load. On the output(s), hand write comments explaining what's happening and what you are testing and why it is functioning correctly.