Lab 5
CSCI 320 Computer Architecture
Integer Multiply Instruction
September 25, 2007

Purpose: To design an integer multiply instruction in Verilog HDL.

Preparation for Lab: Read pages I-2 to I-7 of Computer Architecture: A Quantitive Approach by Hennessy and Patterson, Fourth Edition. This Appendix is NOT in the book but on the CD. A local copy is on-line at 

     ~cs320/appendix-I.pdf

Laboratory: Copy the Verilog HDL code of the ULTRA3 computer of the end of Lab #3 to a new machine ULTRA5.

Don't forget your design decisions log.

Add the following instruction to your ULTRA5 computer.

   MUL Ri,Rj,Rk  Integer MULtiply.  Multiply the value of the Rj
                 by the value in Rk and place the result in the Ri.  
                 If overflow, set the mof flip flop to 1 otherwise 0.
	         If overflow, set Ri to 0.
Assume negative numbers are represented in 2's complement. If one or both numbers are negative, convert them to positive numbers before multiplying. If both signs are same, the result is positive. If either is negative, convert the result to a negative number.

Do the multiplication by repeatedly shifting and adding (see pages I-4 and I-5). Note that multiplying two 15-bit numbers may produce a 30-bit result. Assume for this lab, if the result is ever greater than 15 binary digits, the machine has overflow and the machine should set the multiply overflow flip flop (mof) to a 1 and set Ri to 0.

Hand In:

Hand in the following cases:

	1.  5 times 6
	2. -5 times 6
	3.  5 times -6
	4. -5 times -6
	5. 128 times 128
	6. 128 times 256
	7. 256 times 256
	8. 128 times 0
Hand in the Verilog code and the outputs including the mof register in hex with hand written comments explaining how the your tests show that your multiply instruction is working correctly.

Save your working ULTRA5 for a later lab.
Page maintained by Dan Hyde, hyde at bucknell dot edu Late update September 23, 2007
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