Reference: Pages 80-89 in Computer Architecture: A Quantitative Approach by John L. Hennessy and David A. Patterson, fourth edition, Morgan Kaufmann, 2007.
Laboratory
Copy the final version of your Ultra from Lab 3 to a new file, say ultra8.v. This is the version where you added the branch instructions to your processor.
You are to add a simple 2-bit predictor scheme to your Ultra. We will not add dynamic scheduling or any other sophisticated scheme to our processor but only implement branch prediction and gather statistics.
Assume the Branch History Table (BHT) has 8 entries. What do you think the BHT should be initialized to? In the IF stage add code to predict if one of the three branch instructions will be taken or not.
In each of the three branch instructions, add code to properly update the BHT. Use the state diagram on page 83 for your implementation. Since the same code will be used in three different places, this an ideal time to use a Verilog "task". Read about Verilog's tasks in the Verilog Manual and implement a task for updating the BHT.
Gather statistics on how many branches were executed, how many were predicted to be taken and how many were predicted correctly.
Add a new op code for a Halt instruction. The Halt instruction displays the statistics and then executes a $stop; command.
Notice that in Verilog one can not read a single individual bit in a rectangular structure, e.g., Mem or R, the register file. One must do a read of the"word" in the memory and transfer result to a register. Then one can access a bit of the register, e.g., MD[1].
Design your own simple test program to convince yourself that your branch prediction works and gathers the correct statistics.
Handin
A listing of your working Ultra 8 and a run of the following program.
Data 2
Data 1
Data 9
Load R1,4 // R1 HOLDS 1
Load R2,3
Load R3,5 // R3 holds 9
Add R2,R2,R1
BEQ R1,R2,4
Add R2,R2,R1
Add R2,R0,R1
BNE R1,R2,-3
SUB R3,R3,R1
BNE R3,R0,-6
Halt