Purpose: To design and implement a cache memory system for the ULTRA3.

Reference: Computer Architecture: A Quantitative Approach, by John Hennessy and David Patterson, Morgan Kaufmann, Fourth Edition, 2007, pages C-1 to C-15.

This laboratory has two parts. In the first part, you are to design a cache memory system for the ULTRA3 (the final machine of Lab 3).  In the second part, you are to implement your design in Verilog HDL.

Part 1: Design the Cache

The ULTRA3's memory has 256 16-bit words. Assume now that to access memory, it takes 20 clock periods (modeled by #(20*clock) MD <= MEM[MA];) and we have added a level 1 unified cache memory between the memory and the CPU. You may access the cache in one clock period, i.e., #clock MDC <= CACHE[MAC];. The block size is 4 words, i.e., 64 bits; and, you may now access a whole block from memory at one time and move it to the cache. The cache size is 8 block frames (cache slots or lines). The write through cache is directly mapped and uses no-write-allocate on a write miss.

Your design should include:

1. A diagram showing the structure of the cache including the names of the fields and size of the fields.
2. Show the structure of an address request from CPU from viewpoint of cache (name of fields and size of fields) [similar to Fig C.3 on page C-8].
3. Evidence that you considered cache hits and cache misses, and reads and writes.
   

Part 2: Implement the Cache

Copy the Verilog HDL code of the ULTRA3 computer of Lab 3 to a new file ULTRA10.v.

Modify the new file, containing the new ULTRA10, to implement your design of Part 1.

Details:

1. You will need to perform the mod operation in Verilog HDL. If one is performing mod of a power of two, one does not need to use the % operator. For example, if we want A mod 8, we just use the last three right hand bits of register A.
2. You can't access a range of bits of a memory in Verilog HDL. For example, there is NO way to do this: CACHE[3][5:6]. You must transfer a copy of the word in storage (memory or cache) to a register and then access the range of bits in the register.
3. You will need to modify Memory MEM to have 64 "superwords" (64 bits wide, i. e., a block). Therefore, you will need to modify the software program below from 16-bit words to 64 bit "superwords".  A 64 bit superword would have four 16-bit words concatenated.  Your first superword would hold the contents of your current MEM[0], MEM[1], MEM[2] and MEM[3].  This is something you will hard code into your program, not something that you will ask Verilog to do.                                                                                                                                                   
   
4. Add Verilog tasks for cache reads and cache writes. This can be done for a cache read by placing all the code in a task block as shown:

       task CacheRead;
           begin
              // code for cache read
           end
       endtask
   

   before and outside the always construct. Now in the proper places in your program you call the task by

        CacheRead;
   

   All identifiers, e. g., registers, are global across the module including the task. Make sure you set the registers properly between calls to CacheRead.

HAND IN

Perform the following test program. The PC starts at 10. Run the program so that it loops back to address 11 three times.

	 3 	Data 	2 
	 4	Data	1 
	10	Load    R1,3
	11	Load    R2,4
	12 	Add	R1,R1,R2 
	13	Store	R1,5 
        14	Jump	11