Computer Science Department, Bucknell University

CSCI 320 Computer Architecture
Verilog HDL

The hardware description language Verilog HDL is being used for the laboratories in CSCI 320. Since CSCI 320 is a computer architecture course, we are focusing on the behavioral level of Verilog to explore the architectural characteristics of digital systems. Professor Dan Hyde wrote a short 32 page manual which we use in the course called "CSCI 320 Computer Architecture Verilog HDL Manual."

Also, Professor Dan Hyde wrote a 12 page discussion of the Model of Computation used in the course and how the Verilog HDL code subset we use is realized in digital logic circuits. A PDF version of Realization of Verilog HDL Computation Model is available.

In the course, we use the Verilog HDL simulator originally written by Wellspring Solutions, Inc. called VeriWell. VeriWell is now distributed and sold by SynaptiCAD Inc. For Windows 95/NT, Windows 3.1, Macintosh, SunOS and Linux platforms, SynaptiCAD Inc. offers FREE versions of their VeriWell product available from http://www.syncad.com/ver_down.htm. The free versions are the same as the industrial versions except they are restricted to a maximum of 1000 lines of HDL code. Included in their documentation is the VeriWell User's Guide.

Professor Dan Hyde presented a paper on "Using Verilog to Teach Computer Architecture Concepts" at the Computer Architecture Education Workshop as part of the 25th Annual International Symposium on Computer Architecture in Barcelona, Spain, June 29, 1998 (pdf format). Also, on-line are the vugraphs of his talk (pdf format).

See the special IEEE Micro issue on Computer Architecture Education, May/June 2000 where Professor Dan Hyde has a paper "Teaching Design in a Computer Architecture Course," pages 23-28.

Books on Verilog HDL

1. Open Verilog International (OVI), Verilog HDL Language Reference Manual (LRM), 15466 Los Gatos Boulevard, Suite 109-071, Los Gatos, CA 95032; Tel: (408)353-8899, Fax: (408) 353-8869, Email: OVI@netcom.com, $100.

2. Sternheim, E. , R. Singh, Y. Trivedi, R. Madhaven and W. Stapleton, Digital Design and Synthesis with Verilog HDL, published by Automata Publishing Co., Cupertino, CA, 1993, ISBN 0-9627488-2-X, $65.

3. Thomas, Donald E., and Philip R. Moorby, The Verilog Hardware Description Language, second edition, published by Kluwer Academic Publishers, Norwell MA, 1994, ISBN 0-7923-9523-9, $98, includes DOS version of VeriWell simulator and programs on diskette. Philip Moorby was the original designer of Verilog HDL back in 1985.

4. Bhasker, J., A Verilog HDL Primer, Star Galaxy Press 1058 Treeline Drive, Allentown, PA 18103, 1997, ISBN 0-9656277-4-8, $60.

5. Palnitkar, Samir, Verilog HDL: A Guide to Digital Design and Synthesis, Prentice Hall, Upper Saddle River, NJ. 1996. 396 pp. ISBN 0-13-451675-3 ($75 as of 10/98) Palnitkar's book comes with a CD-ROM with Silos III student edition. (There may be a cheaper book without the CD-ROM, I didn't see it as an option). Bill Nelson has used Silos in class and says it is good. The Verilog Usenet newsgroup FAQ speaks highly of Silos III.

A list of books on Verilog HDL maintained by Gerard M. Blair.

WWW Sites on Verilog HDL

FAQ for comp.lang.verilog

Cadence Design Systems, Inc.

Verilog Research at Cambridge, England

Rajesh Bawankule's Verilog Page

Page written by Dan Hyde, hyde at bucknell.edu Last update August 7, 2007