The first feedback loop is the master and the second is the slave.
The way the clocks are inputted, this is a positive edge triggered
flip flop. This design is very similar to the D flip-flop design on page XXX of
the textbook. However, a Clear control input is added in the master
loop. The positioning of the Clear control here in the design allowed
for compactness and conserved transistors. In order to make the
Clear input sychronous, it first must be NANDed with the clock. Also,
an enable input was included by effectively ANDing the clock with an
Enable control input. When Enable is high, the clock runs and data is
transmitted. If Enable is low, the clock is off and nothing
happens(including clear). The updated register design, complete with
Enable and Clear controls, is in the file dreg12. This file has been
extracted and simulated and produces good results. 16 and 5 bit
registers without all of the proper control inputs can be found in
dreg10 and dreg11, respectively.
The basic IC layout is shown below:
This picture shows one flip-flop out of the 16 flip-flops within the
register. If you inspect the above picture you can see that the first
D flip-flop input comes in at the unconnected bottom-left
purple branch as metal 2. The corresponding Q output branches off at
the top-right purple layer of metal 2. The purple branch at the bottom
right of the picture is the D input to the next flip-flop. The logic
before the D flip flop is the NAND gate and inverter for the Enable
control. Every register in the recognition system uses the above D
flip-flop design. This design worked well and ran easily at speeds greater
than 1 Mhz.
After the registers clock in the reference matrix and the input matrix, it's necessary to know how many of the input matrix squares differ from the corresponding reference matrix squares. Using a simple XOR gate accomplishes this.
Page designed and maintained by Chris Tassone:tassone@bucknell.edu
