Pattern Recognition System

2 Input XOR Gate

The XOR design team went through several different implementaions of this logic gate. From XORs that used 6 MOS transistors to disgustingly large designs. The 6 MOS transistor design seemed really simple. It was an ingenious logic design that we found in one of our logic books. But after we layed it out in Magic, we realized that we had a big problem with gate/source/drain areas. The layout was very tricky and required advanced knowledge of dynamic CMOS logic, so we decided to scrap it.

The excessively large designs were exact implementations of an XOR gate from the most basic logic-level design. We thought that designing a more complex IC-level gate from it's most basic logic-level design would help to utilized our basic building block library of NANDs, NORs, and inverters. In terms of complexity, it turned out that the design we decided on fell in the middle of the previous two, and is shown below:

And the corresponding IC layout is:

The above design is referred to as a pass-gate XOR, because of it's use of transmission gates. It works very well, and it's very fast. Response times for this gate ranged from 1ns to 3ns for falltimes and risetimes, respectively. So, we're talking about roughly 300 Mhz to 1 Ghz, not too bad. And it meets the MOSIS space constraints with 16 cascaded XORs.

The outputs of the XORs give us an indication of whether or not corresponding matrix elements were equal. If the corresponding squares stayed the same color, then the XOR outputs a 0. If they change, then the XOR will output a 1.

So, how do we figure out how many of the squares changed? These 16 parallel XOR outputs are then taken to the counter.

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