ELEC 101

Prof. Rich Kozick

February 26, 1998

Prof. Rich Kozick

February 26, 1998

Thevenin Equivalent Circuit Models

In this lab, we will develop Thevenin equivalent circuit models for a digital logic gate. We will begin by learning how to read the data sheet for the digital logic gate.

You may find it useful to review the
electronic lesson on Thevenin equivalent circuit models
in the `Exploring Engineering` program.

Your lab kit includes a chip labeled 7400 that contains four NAND gates. (The actual label on the chip may be 74LS00 or 74ALS00.) The data sheet that describes the 7400 chip is attached. (You can view data sheets for a variety of NAND gate circuits atINPUTS OUTPUT A B Y 0 0 1 0 1 1 1 0 1 1 1 0

**Before lab**, please read the attached data sheet for the 7400
chip and
try to answer the following questions.

- What is the allowed range of
*input*voltage levels to represent a 0 or logical low? - What is the allowed range of
*input*voltage levels to represent a 1 or logical high? - At the
*output*of the logic circuit, what range of voltage levels are produced to represent a 0 (low) and a 1 (high), respectively? - Suppose that the output of a NAND gate is connected to the input
of another NAND gate.
When the first NAND gate output is a 1, how much current flows
between the gates? In which direction does the current flow?
(The convention for the sign of the current in the data sheet is that
positive current flows
*into*the device.) - Repeat the previous question when the first NAND gate output is a 0.
- Is there any limit on how many gates a given output can be "fanned-out" to? Is the limit more restrictive in the case of a 0 output or a 1 output? Please explain.

I have prepared a MATLAB program
`dplot.m`
to help you plot your data and obtain the Thevenin model parameters
by fitting a straight line to your data.
Save the program `dplot.m` on the PC,
start MATLAB on the PC, and open the file
`dplot.m` in the editor.
Enter your data, and follow the instructions in the program.

Can your data be well-approximated by a straight line? (You may want to use only a subset of your data to obtain the Thevenin model.) What is a reasonable Thevenin model for the NAND gate producing a 1 at its output?

**Discuss your results with the instructor**, and then perform
the following.

- According to the data and Thevenin model that you constructed above, how much current must be drawn from the NAND gate output so that the output voltage is no longer within the limits of a logical 1?
- Develop a Thevenin model for the NAND gate output for the case when the NAND output is a logical 0. Is the model different from the case when the NAND output is a 1?
- Is it possible to obtain a Thevenin model for the
*input*to the NAND gate? You might begin to answer this question by measuring the open-circuit voltage at an*input*to a NAND gate on the 7400 chip. What is the Thevenin model for this case? - Can you apply your Thevenin models to explain the "fan-out" limit discussed in Section 1 of this lab?