ELEC 101, Spring 2005
Prof. Rich Kozick
Date Assigned: Monday, April 25, 2005
Date Due: Monday, May 2, 2005
Please continue to study Chapter 12 (all sections)
and Chapter 13, Sections 13.1 and 13.2
- Final Exam:
The final exam for ELEC 101 is scheduled for Thursday, May 5 at 3:30
PM in room Dana 137.
The exam will be comprehensive, and you will be allowed to bring
a page of notes with you.
I will also collect your lab notebooks at the final exam.
- Please solve Problem 12.34 in the Bobrow text.
Design a 2-bit UP-counter using D flip-flops. Your circuit should
operate as follows:
[CIRCUIT DIAGRAM IS NOT AVAILABLE IN HTML DOCUMENT.]
The outputs S1 S0 are the count: 00, 01, 10, or 11. When C = 1, then
the output should increment by one with each clock pulse. The count
should wrap-around to 00 after 11. When C = 0, the present count
should be held.
Explain your reasoning, and draw a diagram for your design.
(Hint: Construct a state diagram, then a state transition table,
and finally design appropriate combinational logic circuits.)
- Repeat the previous design using JK flip-flops.