Everyone should prepare solutions to be submitted on the specified due dates. The leaders will explain their solutions to the class on the due dates. We will spend some time during class this week working on these problems. Please work on the problems this week and bring your questions to class.

Reading for the week of February 15: We will begin studying sequential circuits this week. Please read Chapter 4, sections 4-1 through 4-3.

1. Consider the adder-subtractor circuit shown in Figure 3-30 of the text. Suppose the 4-bit inputs
   A₃ A₂ A₁ A₀ and B₃ B₂ B₁ B₀ are unsigned binary numbers. In other words, the decimal equivalents of the input values are 0, 1, ..., 15. The circuit will add the inputs if S = 0 and subtract B from A when S = 1.

   Design a circuit that will convert the output C₄ S₃ S₂ S₁ S₀ to the corresponding number in 5-bit signed magnitude representation. In addition, you should detect when overflow errors occur.

   Your circuit should output 6 binary values: V to indicate overflow, 1 sign bit G, and 4 bits
   M₃ M₂ M₁ M₀ for the magnitude. You can assume that full adders are available for use in your circuit, as well as other logic gates (AND, OR, NOT, etc.).

   You may find it useful to begin by considering some particular input values and finding the desired outputs from your circuit. What is the range of output values that can be achieved with no overflow? How will you detect overflow?

   Due on Monday, February 22. Leaders to present solution: Travis Harkness, Ron Hess, and Valter Karavanic.

2. Again consider the adder-subtractor circuit shown in Figure 3-30 of the text. Now suppose that the 4-bit inputs A₃ A₂ A₁ A₀ and B₃ B₂ B₁ B₀ are in signed 2's complement format. In other words, the decimal equivalents of the input values are -8, -7, ..., +7.

   Design a circuit to perform the same operation described in question 1. You may find it useful to begin by considering some particular input values and finding the desired outputs from your circuit. What is the range of output values that can be achieved with no overflow? How will you detect overflow?

   Due on Monday, February 22. Leaders to present solution: Heidi Daub, Jennine Witherup, and Rodney Young.

3. The block diagram for a BCD adder is shown in Figure 3-34 on page 153 of the text. Please explain all of the steps and reasoning used to design this circuit. Show K-maps to explain the design of the combinational logic in the circuit.

   Due on Wednesday, February 24. Leaders to present solution: Jennie Goossen, Brian Green, and Sarah Gunnels.

4. Design a binary multiplier that multiplies two 4-bit numbers (this is called a 4-bit by 4-bit multiplier). Use 4-bit binary adders and AND gates in your design. Show the complete logic circuit diagram. Refer to Section 3-11 of the text for a discussion of binary multiplier design.

   Due on Wednesday, February 24. Leaders to present solution: Alex Rudis, Rocco Russo, and David Seiler.

   Extra Credit: Design a binary multiplier that multiplies two 8-bit numbers (i.e., a 8-bit by 8-bit multiplier). Use 4-bit by 4-bit multipliers, adders, and additional logic in your design. You don't necessarily need to provide a complete logic diagram (since it can get tedious and complicated to do by hand), but try to explain the basic idea that allows 8-bit by 8-bit multiplication to be performed with 4-bit by 4-bit multiplier subsystems and 4-bit adders. (Hint: try to work an example by hand.)

Thank you.