======================================================================= From Amy Tran's presentation: "The Intel Architecture" 1. What are the three steps in dynamic execution? Answer: These three steps are: * Multiple branch prediction: Predicts program execution through several branches, thereby accelerating the flow of work to the processor * Dataflow Analysis: Creates an optimized, reordered schedule of instructions by analyzing data dependencies between instructions * Speculative execution: Carries out instructions speculatively and based on this optimized schedule, ensures that the processor's superscalar execution units remain busy, thereby boosting overall performance. 2. What are the effects on the streaming SIMD Extensions : Answer: Some of the benefits to the desktop and Intel Applications are: - Higher resolution and quality images can be viewed and manipulated previously possible - High quality audio, MPEG2 video, and simultaneous MPEG2 encoding and decoding - Reduced CPU utilization for speech recognition, as well as higher and faster response times ======================================================================= From Junita Palomar's presentation: " The Athlon Processor" 1. What is the total amount of cache on the Athlon processor? Answer:AMD Athlon processors has a large dual-ported 128KB split-L1 cache (64KB instruction cache + 64KB data cache); a high-speed 256KB (full-speed, on-chip) or 512KB L2 cache (off-chip with support for up to 8MB). Total of 384K 2. How many total instructions are there in Athlon's Enhanced 3DNow! Technology? Answer: 24 New Instructions of Enhanced 3DNow! Technology 21 Original Instructions of Enhanced 3DNow! Technology -- Total 45 ======================================================================= From Josue Rivas's presentation: "PCI Bus" 1. What is one advantage of the PCI design? Answer: One advantage to the PCI design is that up to 256 devices can be attached to one PCI local bus, and up to 256 PCI busses can exist in one system. 2. What does the PCI BIOS do? Answer: The PCI BIOS initializes and maintains the environment of the PCI BUS. ======================================================================= From Jaime Guerra's presentation: "Crusoe: A New Idea" 1. What is the difference between Code Morphing and emulation? Answer: Code Morphing is a recompilation of the X86 code into Crusoe instructions which happens in large blocks of code. Emulation is an interpretation of X86 code one instruction at a time. 2. How does putting logic in software save energy? Answer: The more logic you put in the software the less logic you need in the hardware. Less logic in hardware means less transistors,less transistors less power consumption. ======================================================================= From Damian Benavides' presentation: "AMD Athlon vs. Intel Pentium III" 1. With the rapidly growing technological advances today, which system would be more cost efficient: the AMD Athlon 1 GHz or the Intel Pentium III 8000 MHz? Answer: Because AMD Athlon's performance on a 1 GHz processor is only a tad faster than the 800 MHz Pentium, it would probably be a better choice to go with the Pentium. The luxury price of the 1 GHz CPU is not worth it. 2. The AMD Athlon is equipped with a 200 MHz bus yet it is limited in most cases to 100 MHz, why is that? Answer: The 200 MHz bus is only utilized by the Athlon's northbridge in early models and is limited to 100 MHz according to the speed of the memory. Recent development have boosted it to 133 MHz. ======================================================================= From Hector Leal's presentation: "the Pentium Processor about Pipelineing, Branching and Cache" 1. What are the two integer pipelines called and what instructions does each take? Answer: The pipelines are called u and v pipes. The u-pipe can execute any instruction in the Intel achitecture, while the v-pipe can execute simple instructions which are instructions that are entirely hardwired and do not require any microcode and in general execute in one clock. 2. List and briefly explain the five stages of an integer pipeline? - Prefetch (PF) - stage in which instructions are prefetched from the on-chip instruction cache or memory. - Decode 1 (D1) - stage in which two parallel decoders attempt to decode and issue the next two sequential instructions. - Decode 2 (D2) - stage in which addresses of memory resident operands are calculated. - Execute (EX) - stage of the pipeline for both ALU operations and for data cache access. - Writeback (WB) - stage where instructions are enabled to modify processor state and complete execution. ======================================================================= From Josephy Resurreccion and Ray Reyna's presentation: "The AMD Athlon Processor" 1. What are the new 21 additional instructions added to the 3D Now instructions? 2. What is the significance of having a larger L1 cache? Note: Joe and Ray didn't give us the answers. I am asking for the answers from them.