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Project 3 – Research Project

Project Description This project is the culminating experience for the course. For this project, you have the opportunity to further explore (research and implement) a topic in computer architecture. Option 1 – Verilog CPU Advanced Feature After completing the pipelined

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Project 1 – Single Cycle MIPS

Due: Friday, 9/15/2017. The goal of this project is to implement the MIPS single cycle CPU from activity 06. This header file defines many/all of the MIPS bits/vectors and is useful when completing this assignment. Below is how to include

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Project 2 – Pipelined CPU

Project Description In this project you will develop a Behavioral Verilog model for a pipelined MIPS CPU. You will implement the standard 5-stage pipeline (fetch, decode, execute, memory, writeback) with EX-EX, MEM-EX, and MEM-MEM forwarding and hazard detection logic. If a

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Project 0 – Lab Intro

Goals Setup your Verilog environment. Know how to use Icarus Verilog and GTKWave for Verilog simulation and visualization. Introduction Verilog is an IEEE standard that defines a language used to describe digital systems. There is a whole Wikipedia page full

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