Blog Archives

Project 3 – Research Project

Project Description This project is the culminating experience for the course. For this project, you have the opportunity to further explore (research and implement) a topic in computer architecture. Option 1 – Verilog CPU Advanced Feature After completing the pipelined

Posted in Projects Tagged with:

Project 2 – Pipelined CPU

Project Description In this project you will develop a Behavioral Verilog model for a pipelined MIPS CPU. You will implement the standard 5-stage pipeline (fetch, decode, execute, memory, writeback) with EX-EX, MEM-EX, and MEM-MEM forwarding and hazard detection logic. If a

Posted in Projects Tagged with: , ,