/* 
 * NatSemi PC16550D Uart - Laddie IO Specification 
 * Author: Lea Wittie
 * Copyright (c) 2007 Bucknell University
 *
 * Permission is hereby granted, free of charge, to any individual or
 * institution obtaining a copy of this software and associated
 * documentation files (the "Software"), to use, copy, modify, and
 * distribute without restriction, provided that this copyright and
 * permission notice is maintained, intact, in all copies and supporting
 * documentation.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
 * IN NO EVENT SHALL BUCKNELL UNIVERSITY BE LIABLE FOR ANY CLAIM, DAMAGES
 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
 * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */

integer DLAB [0:1];

port 0 { name=RBR; size=1; access=read;
 requires DLAB==0;
}
port 0 { name=THR; size=1; access=write;
  requires DLAB==0;
}
port 0 { name=DLL; size=1; access=readwrite;
  requires DLAB==1;
}

port 1 { name=IER; size=1; access=readwrite;
 [0] ERBFI;
 [1] ETBEI;
 [2] ELSI;
 [3] EDSSI;
  requires DLAB==0;
}
port 1 { name=DLM; size=1; access=readwrite;
  requires DLAB==1;
}

port 2 { name=IIR; size=1; access=read;
 [0] IntPending;
 [1:3] IntID;
 [6:7] FifosEnabled;
}
port 2 { name=FCR; size=1; access=write;
 [0] FifoEnable;
 [1] RcvrFifoReset;
 [2] TxmitFifoReset;
 [3] DMAModeSelect;
 [6] LSB;
 [7] MSB;
}
port 3 { name=LCR; size=1; access=readwrite;
  [0:1] WLS;
  [2] STB;
  [3] PEN;
  [4] EPS;
  [5] StickParity;
  [6] SetBreak;
   [7] dlab;
  ensures DLAB==DLAB;
}
port 4 { name=MCR; size=1; access=readwrite;
  [0] DTR;
  [1] RTS;
  [2] Out1;
  [3] Out2;
  [4] Loop;
}
port 5 { name=LSR; size=1; access=readwrite;
  [0] DR;
  [1] OE;
  [2] PE;
  [3] FE;
  [4] BI;
  [5] THRE;
  [6] TEMT;
  [7] RcvFifoError;
}
port 6 { name=MSR; size=1; access=readwrite;
  [0] DCTS;
  [1] DDSR;
  [2] TERI;
  [3] DDCD;
  [4] CTS;
  [5] DSR;
  [6] RI;
  [7] DCD;
}
port 7 { name=SCR; size=1; access=readwrite;
}