04 – Single Cycle MIPS

Handout 04 – Single Single MIPS Datapath

Activity 04 – MIPS Encoding and Jump Control

MIPS Green Sheet (Bucknell Only)

 

Hello everyone,

  • I will look into changing the activity submission to gitlab by Friday. We will try to set that up Thursday.
  • Friday is an extra lab-ish day, to continue Project 1 work. The 10AM class will meet in Dana 213. The 2PM class will meet in the regular Breakiron 164 location. Please remember Project 1 is an individual assignment.
  • On Activity 4:
  1. lw and sw (load word and store word) are I-type instructions, meaning they include a constant (immediate) 16-bit value.  These particular I-type instructions would of course interact with the data memory, as opposed to the implication of slide 8 today (drawn up for an addi or li example).
  2. move is a pseudo-instruction equivalent to an add. See P&H 4.14 to note that the funct field (low-order 6 bits) of an add should be 100000.
  3. li should translate to addi, where rt is the destination register.

See you Wednesday. Tomorrow,  Tuesday, I should be available 10-12 and after 3 if you’d like to stop by with anything.

stough

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