05 – Single Cycle MIPS – timing and control

Activity 05 – MIPS Control Signals

mips.h

Hello everyone,

• In tomorrow’s lab we are busy. Goals are to get through Activity 05 together, and to start your individual work on Project 1.
• Notes from today:

1. rs vs rt. Notice that for all I-type instructions that modify a register (l*, ori, addi,…), rt contains the destination register. For store, rt holds the contents to be stored to memory. See here and here.
2. how do we really estimate delays: There are simulation tools, see here, but actual timings can vary widely, see here.
3. You can now find jumps.in in the demo folder. The last hex code there is a jump instruction, x08100000.