08 – Introduction to Multiprocessor Memory

Activity 08 – Multicore Memory Introduction

Hello everyone,

• Activity 08 is due first thing in class on Friday.
• Activity 05 code (control module in Verilog) is due end of the day Friday. Push your code to gitlab and the folder you have shared with me, and I will look at it and make comments over the weekend.
• You will continue working on Project 1 in lab tomorrow.
• Class today

1. Cache characteristics: block {placement, identification, replacement, write strategies}
2. 3 C’s describing the reasons for cache misses: compulsory, capacity, conflict
3. AMAT: average memory access time, the optimization of which is the point of the memory hierarchy to begin with.
4. SMP and local vs shared cache: In multiprocessor systems it is advantageous for individual processors to have local caches high, with a shared cache lower. Given that all processors have access to the same address space for reads and writes, it is important to maintain consistency and coherency with respect to the memory system. See Activity 08 and the slides.