11 – Review of the Pipelined Datapath

Hello everyone,
Lots of notes today

Project:

There is some ambiguity in the project description, apologies: your “Alarm Clock Controller” module has 5 one-bit inputs and 6 outputs. The 6 outputs are: the 4 7’b led drivers; alarm_on (as in whether “the alarm is set”); and buzzer, as in whether “the buzzer is buzzing.” I thought of buzzer as separate from the piezo_buzzer, which would be a 2KHz clock if “the alarm is set” and “the buzzer is buzzing.”
If your example output trace has thousands, or 100K’s of output lines, then in your description you should include the several important timesteps to view through the alarm_view project. Or, you can design your test (and the outputs of your “Alarm Clock Controller” module) to output fewer than 100K’s of lines.

Notes from today: Great questions today in class, several points to make

I’ve added to today’s slides, slide 14, which is a view of the pipelined datapath containing the “pipeline registers.” You think of these registers as containing the outputs of each stage (except WB, whose output is potentially the content of the register file). They’re named by the stages they are between.
MIPS branches are executed during the ID (decode) stage of the five-stage pipeline. See P&H 4.8 (p. 318), which notes there are a couple of consequences to this, in addition to the redundant hardware needs: namely, 1.) the operands of a branch could come from the EX/MEM or MEM/WB pipeline registers, which would contain the result of a previous instruction’s EX or MEM stage; and 2.) two stall cycles are needed in the case of a load followed by a conditional branch on that load result. This is because the operand needed for the conditional branch is not available until the end of the MEM stage of the previous instruction (the load).
There are three forwarding capabilities, EX-EX, MEM-EX, MEM-MEM. EX-EX and MEM-EX can happen during the same cycle (see Activity 11, q2).
Difference between a no-op and a stall: A stall allows previous instructions to continue executing without allowing later instructions allowed to enter the pipeline. A no-op is an instruction that will end up using all five stages of the pipeline, like sll R0, R0, 0 (doing nothing). See here. and here. Clearly these are related concepts.