Project 0 – Lab Intro


Setup your Verilog environment. Know how to use Icarus Verilog and GTKWave for Verilog simulation and visualization.


Verilog is an IEEE standard that defines a language used to describe digital systems. There is a whole Wikipedia page full of Verilog simulators. In this class we will be using Icarus Verilog because it is relatively easy to use and complete (compared to verilator for example). It is also already installed on the lab machines, the executable name is iverilog . Being open source, you can also install it on your own machine. Most Linux distributions provide it as a package called iverilog, you can also download snapshots, or clone the git repo if you’re so inclined.

Getting Started

Now would be a good time to go over to the Icarus Verilog wiki and read the Introduction and go through the Getting Started and Simulation pages.

Move on when you can:

  • Explain the difference between simulation and synthesis.
  • Explain what a testbench file is and when you want/need one.
  • Compile and execute a single file simulation
  • Compile and execute a simulation with multiple files
  • Finish this simulation that uses the $readmemh to load input data into a simulation (we will use this to load programs into our Verilog CPU!) — make sure you understand the output!

Getting Visual

Console output is good for debugging the behavior of your system but it makes timing analysis difficult. To analyze timing, a waveform viewer is very helpful. Fortunately, Icarus (and our lab machines) support GTKWave. Read and complete the Icarus Verilog GTKWAVE tutorial.

To get credit for this lab, show your proficiency with Icarus Verilog and GTKWave by implementing and demonstrating your solution and testbench to activity 02 (min/max/mean) to him in person. 

Read the FAQ

Last but not least, read the FAQ.

That’s all for this week. Next week we’ll begin a real design project.

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