02 – Verilog Primer – part 1

Notes from 8/24:

& vs && for one-bit operands: either is fine (it would evaluate to the same hardware), though & may be more aesthetically pleasing for one-bit input. Be sure to note that && always represents a one-bit signal, whereas & outputs a signal whose bit-width is the maximum of the two operands (bit-wise and). Also note that there is the unary reduction operator & for a single vector input (asking are there any ones in the input signal). See section 6.4 of the Verilog HDL book.
operator precedence can be found in 6.4.11. Note that the conditional operator ?: precedence is very low (it would be executed after all others). Use parentheses to enforce your chosen order of operations.
reg vs net (wire). A reg is not a net! At least, not using the vocabulary of the Verilog book. A reg is a storage element, which can in turn drive the signal on a wire. A wire (net) connects hardware elements, like a reg and a module, or two modules; that is, if a wire is not being driven (through assign, for example), then its value is unknown. See figure 4-4 in particular, slide 25 or section 4.2.3.
reg vs wire, and assignment. Please look at the new links at the bottom of slide 24 noting the differences and similarities. Basically the question is between a continuous assignment (the *assign* keyword) for wire in many scenarios, versus (blocking or non-blocking) procedural assignment of a reg.