Activity 03 – Verilog CPU Building Blocks
A couple of notes from class 03:
- Some question about cycle time versus the simulation timescale. For Activity 3, go ahead and set the timescale as 1ns/1ns. However, given the delays that your modules are to exhibit, the clock should cycle at a different rate.
- Addressing in Activity 3. Apologies for my confusion on the issue. As specified the first PC is 0x00400000. However, that 32-bit address refers to a single byte. The location of the 4-byte block we want to access is given by the high-order 30 bits (so have the memory module accept the high-order 30 bits from the PC–namely 0x00100000 in the first step). To be consistent with the hex file we’re reading in, the “memory” in your memory module should be something like reg [31:0] memory[32’h100000 : 32’h100004], meaning 4 4-byte blocks starting at the location 00100000
- example code used in class is posted in the schedule.
- Many people saw a warning concerning an inconsistency in the standard for readmemh. While this warning does not seem to always show up, it can be eliminated by specifying the beginning and end addressses in the readmemh command (two additional parameters, see 9.5.5 in the Verilog book, and the solution to activity2 in the Demo folder).
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