Activity 03 – Verilog CPU Building Blocks A couple of notes from class 03: Some question about cycle time versus the simulation timescale. For Activity 3, go ahead and set the timescale as 1ns/1ns. However, given the delays that your…
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03 – Verilog Primer – part 2
Posted in Slides Tagged with: Verilog, concatenate, delay, inertial delay, parameters, replicate, slice, transport delay
02 – Verilog Primer – part 1
Activity 02 – Simple Verilog Modules Quick Reference for Verilog HDL Notes from 8/24: & vs && for one-bit operands: either is fine (it would evaluate to the same hardware), though & may be more aesthetically pleasing for one-bit input.…
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